1. Field of the Invention
The present invention relates generally to a semiconductor device. More specifically, the present invention relates to a recess array device and a fabrication method thereof.
2. Description of the Prior Art
For years the trend in the memory industry as well as the semiconductor industry has been to scale down the size of memory cells in order to increase the integration level and thus the memory capacity of DRAM chips. As the cell density of memory devices increases, recess array devices that are formed in recesses in a semiconductor substrate are increasingly favored.
In general, the recess (or gate trench) formed in a substrate has opposing sidewalls and a bottom surface extending between the sidewalls. A gate oxide layer is formed in the recess. A gate structure is then deposited into the recess. Doped regions may then be formed in the main surface of the substrate to form source and drain regions.
The prior art recess array devices still have some drawbacks. For example, the prior art recess array devices is subject to higher gate-induced drain leakage (GIDL) currents in the vicinity of the overlap region between the gate and the drain region. GIDL current in the overlap region may be caused by band to band tunneling effects, and can impose significant operating limitations on thin-oxide cell devices and loss of retention time performance. Although the GIDL current in the overlap region can be alleviated by increasing the thickness of the gate oxide layer, the write back performance on the other hand would be compromised.
Therefore, there is a need in this industry to provide an improved recess array device that is capable of overcoming the above-mentioned shortcomings.